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fedl64p168-01 semiconductor ML64P168 4-bit microcontroller with built-in rc oscillation type a/d converter and lcd driver 1/51 this version: sep. 27,1999 previous version: jun. 22,1999 general descr i p t i o n the ML64P168 is a one-time-programmable rom-version product, which has one-time prom (otp) as internal program memory. on the other hand, the ml64168 is a mask rom-version product, which has mask rom as internal program memory. unlike the mask rom-version product (ml64168), the ML64P168 cannot be supplied in the form of a chip. the ML64P168 has two operation modes, microcontroller operation mode and prom mode. the microcontroller operation mode is used to operate the ML64P168 like a ml64168 and the prom mode is used to program or read the prom. the ML64P168 is a low power 4-bit microcontroller incorporating the oki?s original cpu core nx- 4/30. the ML64P168 provides a minimum instruction execution time of 4.3 s (@700khz). the ML64P168 contains 8160-byte program memory, 512-nibble data memory, three 4-bit input-output ports, 4-bit input port, 4-bit output port, 2-channel rc oscillation type a/d converter, lcd driver for up to 120 segments, and buzzer output port. a p p l i c a t ion the ML64P168 is best suited for low power, high precision thermometers and hygrometers. f e a tures ? processing speed minimum instruction execution time : 4.3 s @700 khz 91.6 s @32.768 khz ? c l o c k g e n e r a t i o n c i r c u i t low-speed clock : 32.768 khz crystal oscillator high-speed clock : 700 khz rc oscillator ( with an external resistor ) cpu clock is selectable as low-speed clock / high-speed clock by software. ? operating voltage : 1.5 v spec. / 3.0 v spec. ( selectable by mask option ) 1.45 to 1.70 v (1.5v spec.) 2.7 to 3.5 v (3.0v spec.) ? operating temperature : 0 to +65 c the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date.
fedl64p168-01 semiconductor ML64P168 2/51 ? memory space internal program memory : 8160 bytes internal data memory : 512 nibbles ? rc oscillation type a/d converter : 2 channels time division 2-channel method counter a : 1 / ( 10 4 8 ) 1 counter b : 1 / 2 14 1 ? i/o port input-output port : 3 ports 4 bits input port : 1 port 4 bits output port : 1 port 4 bits ( 8 out of the 34 lcd driver outputs can be used as output-only ports by mask option. ) ? lcd driver : 34 outputs (1) at 1/4 duty and 1/3 bias : 120 segments (max.) (2) at 1/3 duty and 1/3 bias : 93 segments (max.) (3) at 1/2 duty and 1/2 bias : 64 segments (max.) voltage regulator for lcd driver (selectable by mask option) the lcd panel display is stable regardless of temporary supply voltage drop, because the voltage generated by the voltage regulator for lcd driver is supplied to the bias voltage generator as a reference voltage. lcd operating voltage when the voltage regulator for lcd driver is used : 3.6 v ( duty cycle = 1/4 or 1/3 ) : 2.4 v ( duty cycle = 1/2 ) when the voltage regulator for lcd driver is not used : 4.5 v ( duty cycle = 1/4 or 1/3 ) : 3.0 v ( duty cycle = 1/2 ) ? buzzer driver : 1 output ( 4 output modes selectable ) ? serial port : synchronous 8-bit transfer selectable as external clock / internal clock selectable as msb first / lsb first ? capture circuit : 2 channels ( 32hz, 64hz, 128hz, 256hz ) ? battery check circuit : 1 ( incorporated into the input-only port ) ? watchdog timer ? interrupt external interrupt : 2 sources internal interrupt : 8 sources ? package: 80-pin plastic qfp ( qfp80-p-1420-0.80-bk ) product name : ML64P168 - xxxgp ( written prom ) ML64P168 - ngp ( blanked prom ) 80-pin plastic qfp ( qfp80-p-1414-0.65-k ) product name : ML64P168 - xxxga ( written prom ) ML64P168 - nga ( blanked prom ) xxx indicates a code number.
fedl64p168-01 semiconductor ML64P168 3/51 program development environment ? structured assembler : sasm64k ? in circuit emulator : ease64168 ? debugger : dt64k
fedl64p168-01 semiconductor ML64P168 4/51 block diagram p1 tr1 tr2 c bias p0 bd capr intc adc 2clk rstc tst bc timing controller siop ir decorder prom 8160 bytes ram 512 nibbles sp tbc bsr halt mief v dd1 v dd2 v dd3 c1 c2 l0 l33 pcm pcl x y h l pch alu b a l1 v ddi int p1.0 p1.1 p1.2 p1.3 bd in0 cs0 rs0 crt0 rt0 in1 cs1 rs1 rt1 osc2 osc1 xt xt rst tst1 tst2 int int 5 cpu core: nx-4/30 tr0 ir romr p2 p3 p4 v ddi int v ddi p0.0 p0.1 p0.2 p0.3 int int data bus ( 8 ) data bus ( 8 ) p2.0 p2.1 p4.3 to lcd wdt address bus to v pp
fedl64p168-01 semiconductor ML64P168 5/51 pin configuration (top view) l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 l14 l15 l16 p2.0 p2.1 p2.3 p3.0 p2.2 l0 l1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p3.1 p3.2 21 22 23 24 p3.3 p4.0 p4.1 p4.2 p4.3 bd v pp v ss rt0 crt0 rs0 cs0 in0 in1 cs1 rs1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 l31 / p6.1 l29 / p5.3 l28 / p5.2 l27 / p5.1 l26 / p5.0 l25 l24 l23 l22 l21 l20 l19 l18 l17 c2 c1 v dd3 v dd2 v ddi l30 / p6.0 63 62 61 64 l33 / p6.3 l32 / p6.2 v dd1 rt1 p0.3 p0.1 p0.0 p1.3 p1.2 p1.1 p1.0 tst2 tst1 reset xt xt v dd osc1 osc2 p0.2 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 77 ( gp : qfp80-p-1420-0.80-bk ) 80-pin plastic qfp
fedl64p168-01 semiconductor ML64P168 6/51 pin configuration (top view) ( continued ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 l14 l15 l16 p2.0 p2.1 p2.3 p3.0 p2.2 l31 / p6.1 l29 / p5.3 l28 / p5.2 l27 / p5.1 l26 / p5.0 l25 l24 l23 l22 l21 l20 l19 l18 l17 c2 c1 v dd3 v dd2 v ddi l30 / p6.0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p3.1 p3.2 p3.3 p4.0 p4.1 p4.2 p4.3 bd v pp v ss rt0 crt0 rs0 cs0 in0 in1 cs1 rs1 rt1 v dd1 l1 l0 p0.3 p0.1 p0.0 p1.3 p1.2 p1.1 p1.0 tst2 tst1 reset xt xt v dd osc1 osc2 l33 / p6.3 l32 / p6.2 p0.2 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 77 ( ga : qfp80-p-1414-0.65-k ) 80-pin plastic qfp
fedl64p168-01 semiconductor ML64P168 7/51 pin descriptions the basic functions of each pin of the ML64P168 is described in table 1. a symbol with a slash ( / ) denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, ? - ? denotes a power supply pin, ? i ? an input pin, ?o? an output pin, and ?i/o? an input- output pin. table 1 pin descriptions ( basic functions ) pin no. function symbol gp ga type description v ss 32 30 - 0v power supply v dd 67 65 - positive power supply v dd1 42 40 - bias output for driving lcd ( + 1.5 v, + 1.2 v* ) v dd2 44 42 - bias output for driving lcd ( + 3.0 v, + 2.4 v* ) v dd3 45 43 - bias output for driving lcd ( + 4.5 v, + 3.6 v* ) v ddi 43 41 - positive power supply for i/o port interface v pp 31 29 - power supply (+12.5 v) for prom writing c1 46 44 - power supply c2 47 45 - pins for connecting a capacitor for generating lcd driving bias xt 69 67 i xt 68 66 o low-speed clock oscillation input and output pins. connect to a crystal ( 32.768 khz ). osc1 66 64 i oscillation osc2 65 63 o high-speed clock oscillation input and output pins. connect to an external resistor for oscillation ( r os ). tst1 71 69 i test tst2 72 70 i input pins for testing. a pull-up resistor is internally connected to these pins. reset reset 70 68 i system reset input pin. setting this pin to l level puts this device into a reset state. then, setting this pin to h level starts executing an instruction from address 0000h. *when the voltage regulator for lcd driver is used.
fedl64p168-01 semiconductor ML64P168 8/51 table 1 pin descriptions ( basic functions ) ( continued ) pin no. function symbol gp ga type description p0.0/ int1/ capin0 77 75 p0.1/ int1/ capin1 78 76 p0.2/ int1 79 77 p0.3/ int1/ cmp 80 78 i 4-bit input port ( port 0 ) selectable as pull-up resistor input, pull-down resistor input, or high impedance input by the port 01 control register ( p01con ). p1.0 73 71 p1.1 74 72 p1.2 75 73 p1.3 76 74 o 4-bit output port ( port 1 ) selectable as nmos open drain output or cmos output by the port 01 control register ( p01con ). p1.0 is a high current drive output port. p2.0/ int0 18 16 p2.1/ int0 19 17 p2.2/ int0 20 18 p2.3/ int0 21 19 i/o 4-bit input-output port ( port 2 ) fllowing can be specified for each bit by the port 2 control registers 0 to 3 ( p20con to p23con ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) nmos open drain output or cmos output p3.0/ int0 22 20 p3.1/ int0 23 21 p3.2/ int0 24 22 p3.3/ int0/ sin 25 23 i/o 4-bit input-output port ( port 3 ) following can be specified for each bit by the port 3 control registers 0 to 3 ( p30con to p33con ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) nmos open drain output or cmos output p4.0/ int0/ sout 26 24 p4.1/ int0/ spr 27 25 p4.2/ int0/ sclk 28 26 ports p4.3/ int0/ mon 29 27 i/o 4-bit input-output port ( port 4 ) following can be specified for each bit by the port 4 control registers 0 to 3 ( p40con to p43con ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) nmos open drain output or cmos output
fedl64p168-01 semiconductor ML64P168 9/51 table 1 pin descriptions ( basic functions ) ( continued ) pin no. function symbol gp ga type description buzzer bd 30 28 o output pin for the buzzer driver. rt03331o resistance temperature sensor connection pin ( for channel 0 ) crt0 34 32 o resistance/capacitance temperature sensor connection pin ( for channel 0 ) rs0 35 33 o reference resistor connection pin ( for channel 0 ) cs0 36 34 o reference capacitor connection pin ( for channel 0 ) in0 37 35 i input pin for rc oscillator circuit ( for channel 0 ) rt14139o resistance temperature sensor connection pin ( for channel 1 ) rs1 40 38 o reference resistor connection pin ( for channel 1 ) cs1 39 37 o reference capacitor connection pin ( for channel 1 ) a/d converter in1 38 36 i input pin for rc oscillator circuit ( for channel 1 )
fedl64p168-01 semiconductor ML64P168 10/51 table 1 pin descriptions ( basic functions ) ( continued ) pin no. function symbol gp ga type description l0 1 79 o l1 2 80 o l2 3 1 o l3 4 2 o l4 5 3 o l5 6 4 o l6 7 5 o l7 8 6 o l8 9 7 o l9 10 8 o l10 11 9 o l11 12 10 o l12 13 11 o l13 14 12 o l14 15 13 o l15 16 14 o l16 17 15 o l17 48 46 o l18 49 47 o l19 50 48 o l20 51 49 o l21 52 50 o l22 53 51 o l23 54 52 o l24 55 53 o l25 56 54 o lcd segment and common signals output pins. l26 / p5.0 57 55 o l27 / p5.1 58 56 o l28 / p5.2 59 57 o l29 / p5.3 60 58 o l30 / p6.0 61 59 o l31 / p6.1 62 60 o l32 / p6.2 63 61 o lcd driver l33 / p6.3 64 62 o lcd segment and common signals output pins. these pins can be configured to be output ports by a mask option.
fedl64p168-01 semiconductor ML64P168 11/51 table 2 pin descriptions ( secondary functions ) pin no. function symbol gp ga type description p2.0/ int0 18 16 p2.1/ int0 19 17 p2.2/ int0 20 18 p2.3/ int0 21 19 i p3.0/ int0 22 20 p3.1/ int0 23 21 p3.2/ int0 24 22 p3.3/ int0 25 23 i p4.0/ int0 26 24 p4.1/ int0 27 25 p4.2/ int0 28 26 p4.3/ int0 29 27 i secondary functions of p2.0 to p2.3, p3.0 to p3.3, and p4.0 to p4.3: level-triggered external 0 interrupt input pins. the change of input signal level causes an interrupt to occur. p0.0/ int1 77 75 p0.1/ int1 78 76 p0.2/ int1 79 77 external interrupt p0.3/ int1 80 78 i secondary functions of p0.0 to p0.3: level-triggered external 1 interrupt input pins. the change of input signal level causes an interrupt to occur. p0.0/ capin0 77 75 secondary functions of p0.0: this pin is assigned the capture circuit trigger input pin of capr0 function . capture trigger p0.1/ capin1 78 76 i secondary functions of p0.1: this pin is assigned the capture circuit trigger input pin of capr1 function . p3.3/ sin 25 23 i secondary functions of p3.3: this pin is assigned the data input of a serial port. p4.0/ sout 26 24 o secondary functions of p4.0: this pin is assigned the data output of a serial port. p4.1/ spr 27 25 o secondary functions of p4.1: this pin is assigned the ready output of a serial port. serial port p4.2/ sclk 28 26 i/o secondary functions of p4.2: this pin is assigned the clock input-output of a serial port.
fedl64p168-01 semiconductor ML64P168 12/51 table 2 pin descriptions ( secondary functions ) ( continued ) pin no. function symbol gp ga type description rc oscillation monitor p4.3/ mon 29 27 o secondary functions of p4.3: this pin is a monitor output of the rc oscillation clock for an a/d converter and a 700khz rc oscillation clock for a system clock. battery check p0.3/ cmp 80 78 i secondary functions of p0.3: this pin is an analog comparator input pin for battery check circuit.
fedl64p168-01 semiconductor ML64P168 13/51 memory maps program memory ( prom ) interrupt area czp area start address 1fffh 1fe0h 003eh 0020h 0010h 0000h test program area 32 bytes 8160 bytes contents of interrupt area 8 bits 0020h 0.1hz interrupt 0023h 1hz interrupt 0026h 16hz interrupt 0029h 32hz interrupt 002ch 256hz interrupt 002fh a/d converter interrupt 0032h external 1 interrupt 0035h serial port interrupt 0038h external 0 interrupt 003bh watchdog interrupt program memory map address 0000h is the instruction execution start address by the system reset. the czp area from address 0010h to address 001fh is the start address for the czp subroutine of 1- byte call instruction. the start address of interrupt subroutine is assigned to the interrupt address from address 0020h to 003dh. the user area has 8160 bytes of address 0000h to 1fdfh. no program can be stored in the test program area.
fedl64p168-01 semiconductor ML64P168 14/51 data memory the data memory area consists of 8 banks and each bank has 256 nibbles ( 256 4 bits ). the data ram is assigned to bank 6, bank 7 and peripheral ports are assigned to bank 0. bank7 data ram area ( 256 nibbles ) bank0 inaccessible area unused area 7ffh 780h 700h 6ffh 100h 0ffh 080h 07fh 000h sfr area contents of 000h to 07fh 07fh 000h data / stack area ( 128 nibbles ) bank6 data ram area ( 256 nibbles ) 4 bits 512 nibbles 600h data memory map half the bank 7 of data ram area ( 128 nibbles ) is shared by the stack area. the stack is a memory starting from address 7ffh toward the low-order addresses where 4 nibbles are used by subroutine call instruction and 8 nibbles are used by an interrupt. the addresses 080h to 0ffh of bank 0 are not assigned as the data memory, so access to these addresses has no effect. moreover, it is impossible to access bank 1 to bank 5.
fedl64p168-01 semiconductor ML64P168 15/51 absolute maximum ratings ( 1.5 v spec. ) (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd1 ta = 25c -0.3 to + 2.0 v power supply voltage 2 v dd2 ta = 25c -0.3 to + 4.0 v power supply voltage 3 v dd3 ta = 25 c -0.3 to + 5.5 v power supply voltage 4 v ddi ta = 25 c -0.3 to + 5.5 v power supply voltage 5 v dd ta = 25 c -0.3 to + 2.0 v input voltage 1 v in1 v dd input, ta = 25 c -0.3 to v dd + 0.3 v input voltage 2 v in2 v ddi input, ta = 25 c -0.3 to v ddi + 0.3 v output voltage 1 v out1 v dd1 output, ta = 25 c -0.3 to v dd1 + 0.3 v output voltage 2 v out2 v dd2 output, ta = 25 c -0.3 to v dd2 + 0.3 v output voltage 3 v out3 v dd3 output, ta = 25 c -0.3 to v dd3 + 0.3 v output voltage 4 v out4 v dd output, ta = 25 c -0.3 to v dd + 0.3 v output voltage 5 v out5 v ddi output, ta = 25 c -0.3 to v dd + 0.3 v ta = 0 to + 65 c qfp80-p-1420-0.80-bk 381 mw power dissipation pd ta = 0 to + 65 c qfp80-p-1414-0.65-k 334 mw storage temperature t stg - -55 to + 150 c recommended operating conditions ( 1.5v spec. ) (v ss = 0v) parameter symbol condition rating unit operating temperature* t op -0 to + 65 c v dd ,v dd1 - 1.45 to 1.70 v operating voltage* v ddi - 2.70 to 5.25 v external 700khz rc oscillator resistance* r os - 60 to 200 k ? crystal oscillation frequency* f xt - 30 to 35 khz * : at non-regulated lcd driver. in case of select a voltage regulated lcd driver, see p.37/51.
fedl64p168-01 semiconductor ML64P168 16/51 electrical characteristics ( 1.5 v spec. ) dc characteristics ( 1.5 v spec. ) (v ss =0v, v dd1 =v dd =1.5v, v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit +100% v dd2 vo l t a g e * v dd2 c a , c b , c 12 =0.1 f -50% 2.8 3.0 3.2 v +100% v dd3 vo l t a g e * v dd3 c a , c b , c 12 =0.1 f -50% 4.3 4.5 4.7 v crystal oscillation start voltage v sta oscillation start time: within 5 seconds 1.47 - - v crystal oscillation hold voltage v hold - 1.40 - - v crystal oscillation stop detection time t stop - 0.1 - 1000 ms internal crystal oscillator capacitance c g - 10 15 20 pf external crystal oscillator capacitance c gex when external c g used 10 - 30 pf internal crystal oscillator capacitance c d -101520pf internal 700khz rc oscillator capacitance c os - 8 12 16 pf 700khz rc oscillation frequency f osc external resistor r os =160k ? v dd = 1.45 to 1.70v 80 280 350 khz por generation vo l t a g e v por1 when v dd is between v por1 and 1.5v 0-0.4v por non-generation vo l t a g e v por2 no por when v dd is between v por2 and 1.5v 1.4 - 1.5 v 1 battery check reference voltage v rb ta = 25 c 0.50 0.60 0.70 v v rb temperature va r i a t i o n ? v rb - --2- mv/ c 2 notes: 1.?por? denotes power on reset. 2.?t stop ? indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. * : at non-regulated lcd driver. in case of select a voltage regulated lcd driver, see p.37/51.
fedl64p168-01 semiconductor ML64P168 17/51 dc characteristics ( 1.5v spec. ) ( continued ) (v ss =0v, v dd1 =v dd =1.5v, v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max . unit measur- ing circuit supply current 1* i dd1 cpu in halt state (700khz rc oscillation stop) -25 a supply current 2* i dd2 cpu in operating state (700khz rc oscillation stop) -1530 a supply current 3 i dd3 cpu in operating state (700khz rc oscillation in operation) - 200 300 a supply current 4 i dd4 serial transfer, f sck =300khz, cpu in operating state (700khz rc oscillation stop) - 60 100 a r t0 =10k ? - 150 230 a supply current 5 i dd5 cpu in halt state (700khz rc oscillation stop) rc oscillation for a/d converter is in operating state r t0 =2k ? - 600 900 a supply current 6 i dd6 battery check circuit in operating state, cpu in operating state (700khz rc oscillation stop) - 25 125 a 1 * : at non-regulated lcd driver. in case of select a voltage regulated lcd driver, see p.37/51.
fedl64p168-01 semiconductor ML64P168 18/51 dc characteristics (1.5 v spec. ) ( continued ) (v ss =0v, v dd1 =v dd =1.5v, v dd2 =3.0v, v dd3 =4.5v, v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit i oh1 v oh1 = v ddi - 0.5v -6.0 -1.7 -0.7 i ol1 v ol1 = 0.5v 2 5 20 i oh1s v ddi = 5.0v, v oh1s = v ddi - 0.5v -9 -3.0 -1 output current 1 ( p1.0 ) i ol1s v ddi = 5.0v, v ol1s = 0.5v 4 8 25 i oh2 v oh2 = v ddi - 0.5v -6.0 -2.0 -0.7 i ol2 v ol2 = 0.5v 0.7 2.0 6.0 i oh2s v ddi = 5.0v, v oh2s = v ddi - 0.5v -9 -3 -1 output current 2 ( p1.1 to p1.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) i ol2s v ddi = 5.0v, v ol2s = 0.5v 1 3 9 i oh3 v oh3 = v dd - 0.7v -1.8 -0.6 -0.1 output current 3 ( bd ) i ol3 v ol3 = 0.7v 0.2 2 4 i oh4 v oh4 = v dd - 0.1v -1.1 -0.6 -0.2 output current 4 ( rt0, rt1, rs0, rs1, crt0, cs0, cs1 ) i ol4 v ol4 = 0.1v 0.3 0.6 1.1 i oh5 v oh5 = v ddi - 0.5v -1.5 -0.8 -0.15 i ol5 v ol5 = 0.5v 0.15 1.0 4 i oh5s v ddi = 5v, v oh5s = v ddi - 0.5v -2.0 -1.5 -0.2 output current 5 ( when the pins l26 to l33 are configured as output ports ) i ol5s v ddi = 5v, v ol5s = 0.5v 0.2 3.0 5.0 i oh6 v oh6 = v dd - 0.5v -2.1 -0.7 -0.15 output current 6 ( osc2 ) i ol6 v ol6 = 0.5v 0.15 0.7 2.1 ma 2 i oh7 v oh7 = v dd3 - 0.2v (v dd3 level) - - -4 i omh7 v omh7 = v dd2 + 0.2v (v dd2 level) 4 - - i omh7s v omh7s = v dd2 - 0.2v (v dd2 level) - - -4 i oml7 v oml7 = v dd1 + 0.2v (v dd1 level) 4 - - i oml7s v oml7s = v dd1 - 0.2v (v dd1 level) - - -4 output current 7 ( l0 to l33 ) i ol7 v ol7 = v ss + 0.2v (v ss level) 4 - - i ooh v oh = v dd --0.3 output leakage current ( p1.0 to p1.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) (rt0, rt1, rs0, rs1, crt0, cs0, cs1 ) i ool v ol = v ss -0.3 - - a -
fedl64p168-01 semiconductor ML64P168 19/51 dc characteristics (1.5 v spec. ) ( continued ) ( v ss =0v, v dd1 =v dd =1.5v, v dd2 =3.0v, v dd3 =4.5v, v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit i ih1 v ih1 = v ddi ( when pulled down ) 30 90 300 i il1 v il1 = v ss ( when pulled up ) -300 -90 -30 i ih1s v ih1 = v ddi = 5v ( when pulled down ) 80 250 800 i il1s vi l1 = v ss , v ddi = 5v ( when pulled up ) -800 -250 -80 i ih1z v ih1 = v ddi ( in a high impedance ) 0 - 1 input current 1 ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) i il1z v il1 = v ss (in a high impedance ) -1 - 0 i ih2 v ih2 = v dd ( when pulled down ) 2 8 60 i ih2z v ih2 = v dd ( in a high impedance ) 0 - 1 input current 2 ( in0, in1 ) i il2z v il2 = v ss ( in a high impedance ) -1 - 0 i il3 v il3 = v ss ( when pulled up ) -60 -18 -5 i ih3z v ih3 = v dd ( in a high impedance ) 0 - 1 input current 3 ( osc1 ) i il3z v il3 = v ss ( in a high impedance ) -1 - 0 i ih4 v ih = v dd 0-1 a input current 4 ( reset, tst1, tst2 ) i il4 v il4 = v ss -1.0 -0.3 -0.05 ma 3 v ih1 - 1.2 - 1.5 v il1 -0-0.3 v ih1s v ddi = 5.0v 4 - 5 input voltage 1 ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) v il1s v ddi = 5.0v 0 - 1 v ih2 - 1.2 - 1.5 input voltage 2 ( in0, in1, osc1 ) v il2 -0-0.3 v ih3 - 1.2 - 1.5 input voltage 3 ( reset, tst1, tst2 ) v il3 -0-0.3 v4
fedl64p168-01 semiconductor ML64P168 20/51 dc characteristics (1.5 v spec. ) ( continued ) (v ss =0v, v dd1 =v dd =1.5v, v dd2 =3.0v, v dd3 =4.5v, v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit ? v t1 - 0.05 0.1 0.3 hysteresis width ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) ? v t1s v ddi = 5.0v 0.25 1.0 1.5 hysteresis width ( reset, tst1, tst2 ) ? v t2 - 0.05 0.1 0.3 v4 input pin capacitance ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) c in ---5pf1
fedl64p168-01 semiconductor ML64P168 21/51 measuring circuit 1 osc1 r os xt xt 32.768khz crystal c 12 c1 c2 c a ,c b ,c c ,c 12 r os r t0 c s0 r i0 : : : : : 0.1 f 160k ? 10k ? /2k ? 820pf 10k ? osc2 r t0 c s0 r i0 in0 cs0 rt0 a v ddi v dd v ss v dd2 v v dd3 v c a c b v dd1 v c c measuring circuit 2 v dd v dd3 v dd2 v dd1 v ss v ih input *1 v il a *2 output v ddi
fedl64p168-01 semiconductor ML64P168 22/51 measuring circuit 3 v dd v dd3 v dd2 v ss a *3 input output v dd1 v ddi measuring circuit 4 v dd v dd3 v dd2 v dd1 v ss v ih *3 v il *1 input logic circuit to determine the specified measuring conditions. *2 measured at the specified output pins. *3 measured at the specified input pins. input output waveform monitoring v ddi
fedl64p168-01 semiconductor ML64P168 23/51 a/d converter characteristics (1.5 v spec. ) ( v ss =0v, v dd1 =v dd =1.5v, v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measur- ing circuit resistor for oscillation r s0 , r s1 , r t0 , r t0-1 , r t1 c s0 , c t0 , c s1 740pf 2- - k ? input current limiting resistor r i0 , r i1 -110- k ? f osc1 resistor for oscillation =2 k ? 165 221 256 khz f osc2 resistor for oscillation =10 k ? 41.8 52.2 60.6 khz oscillation frequency f osc3 resistor for oscillation =200 k ? 2.55 3.04 3.53 khz kf1 r t0 , r t0-1 , r t1 = 2 k ? 3.89 4.18 4.35 - kf2 r t0 , r t0-1 , r t1 = 10 k ? 0.990 1.000 1.010 - rs ? rt oscillation frequency ratio (*) kf3 r t0 , r t0-1 , r t1 = 200 k ? 0.0561 0.0584 0.0637 - 5 * kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor in the same condition. f oscx (rt0 - cs0 oscillation) f oscx (rt0-1 - cs0 oscillation) f oscx (rt1 - cs1 oscillation) kfx= f oscx (rs0 - cs0 oscillation) , f oscx (rs0 - cs0 oscillation) , f oscx (rs1 - cs1 oscillation) ( x = 1, 2, 3)
fedl64p168-01 semiconductor ML64P168 24/51 measuring circuit 5 r t1 (crosc1) r s1 c s1 r i1 rt1 rs1 cs1 in1 r i0 c s0 r s0 in0 cs0 rs0 c t0 r t0 rt0 crt0 r t0-1 (crosc0) p0.0 p0.1 p0.2 p0.3 oscillation mode designation reset tst1 tst2 v ss d.u.t p4.3 frequency measurement (f oscx ) r t0 ,r t0-1 ,r t1 =2k ? /10k ? /200k ? r s0 ,r s1 =10k ? r i0 ,r i1 =10k ? c s0 ,c t0 ,c s1 =820pf v dd v ddi
fedl64p168-01 semiconductor ML64P168 25/51 ac characteristics (1.5 v spec. ) ( serial interface ) ( v ss =0v, v dd =1.5v , v ddi =2.7v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit sclk input fall time t f - - 15 50 ns sclk input rise time t r - - 15 50 ns sclk input ?l? level pulse width t cwl -0.8-- s sclk input ?h? level pulse width t cwh -0.8-- s sclk input cycle time t cyc -2.0-- s sclk output cycle time t cyc1(o) cpu is operating at 32.768khz - 30.5 - s sclk output cycle time t cyc2(o) cpu is operating at 700khz - 1.43 - s sout output delay time t ddr ---0.4 s sin input setup time t ds -0.5-- s sin input hold time t dh -0.8-- s synchronous communication timing ( ?h? level = 4.0v, ?l? level = 1.0v ) t r t f t cwh t cwl t ddr t ddr t cyc t ds t ds t dh 5v 5v 5v sclk (p4.2) sout (p4.0) sin (p3.3)
fedl64p168-01 semiconductor ML64P168 26/51 absolute maximum ratings (3.0 v spec. ) (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd1 ta = 25c -0.3 to + 2.0 v power supply voltage 2 v dd2 ta = 25c -0.3 to + 4.0 v power supply voltage 3 v dd3 ta = 25 c -0.3 to + 5.5 v power supply voltage 4 v ddi ta = 25 c -0.3 to + 5.5 v power supply voltage 5 v dd ta = 25 c -0.3 to + 4.0 v input voltage 1 v in1 v dd input, ta = 25 c -0.3 to v dd + 0.3 v input voltage 2 v in2 v ddi input, ta = 25 c -0.3 to v ddi + 0.3 v output voltage 1 v out1 v dd1 output, ta = 25 c -0.3 to v dd2 + 0.3 v output voltage 2 v out2 v dd2 output, ta = 25 c -0.3 to v dd3 + 0.3 v output voltage 3 v out3 v dd3 output, ta = 25 c -0.3 to v dd + 0.3 v output voltage 4 v out4 v dd output, ta = 25 c -0.3 to v dd + 0.3 v output voltage 5 v out5 v ddi output, ta = 25 c -0.3 to v dd + 0.3 v ta = 0 to + 65 c qfp80-p-1420-0.80-bk 381 mw power dissipation pd ta = 0 to + 65 c qfp80-p-1414-0.65-k 334 mw storage temperature t stg - -55 to + 150 c recommended operating conditions ( 3.0v spec. ) (v ss = 0v) parameter symbol condition rating unit operating temperature*1 t op -0 to + 65 c v dd - 2.7 to 3.5 v operating voltage*1 v ddi -v dd to 5.25 v external 700khz rc oscillator resistance*1 r os - 60 to 200 k ? crystal oscillation frequency*1 f xt - 30 to 66 khz *1: at non-regulated lcd driver. in case of select a voltage regulated lcd driver, see p.37/51.
fedl64p168-01 semiconductor ML64P168 27/51 electrical characteristics ( 3.0v spec. ) dc characteristics ( 3.0v spec. ) (v ss =0v, v dd2 =v ddi =v dd =3.0v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit +100% v dd1 vo l t a g e * v dd1 c a , c b , c 12 =0.1 f -50% 1.3 1.5 1.7 v +100% v dd3 vo l t a g e * v dd3 c a , c b , c 12 =0.1 f -50% 4.3 4.5 4.7 v crystal oscillation start voltage v sta oscillation start time: within 5 seconds 2.7 - - v crystal oscillation hold voltage v hold - 2.7 - - v crystal oscillation stop detection time t stop - 0.1 - 1000 ms internal crystal oscillator capacitance c g - 10 15 20 pf external crystal oscillator capacitance c gex when external c g used 10 - 30 pf internal crystal oscillator capacitance c d -101520pf internal 700khz rc oscillator capacitance c os - 8 12 16 pf 700khz rc oscillation frequency f osc external resistor r os =60k ? v dd = 2.7 to 3.5v 600 700 1000 khz por generation vo l t a g e v por1 when v dd is between v por1 and 3.0v 0-0.7v por non-generation vo l t a g e v por2 no por when v dd is between v por2 and 3.0v 2.7 - 3 v 1 battery check reference voltage v rb ta = 25 c 0.50 0.60 0.70 v v rb temperature va r i a t i o n ? v rb --2- mv/ c 2 notes: 1.?por? denotes power on reset. 2.?t stop ? indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. *: at non-regulated lcd driver. in case of select a voltage regulated lcd driver, see p.37/51.
fedl64p168-01 semiconductor ML64P168 28/51 dc characteristics ( 3.0v spec. ) ( continued ) (v ss =0v, v dd2 =v ddi =v dd =3.0v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit supply current 1* i dd1 cpu in halt state (700khz rc oscillation stop) -712 a supply current 2* i dd2 cpu in operating state (700khz rc oscillation stop) -3550 a supply current 3 i dd3 cpu in operating state (700khz rc oscillation in operation) - 800 1400 a supply current 4 i dd4 serial transfer, f sck =300khz, cpu in operating state (700khz rc oscillation stop) -4070 a r t0 =10k ? - 300 450 a supply current 5 i dd5 cpu in halt state (700khz rc oscillation stop) rc oscillation for a/d converter is in operating state r t0 =2k ? - 1200 1800 a supply current 6 i dd6 battery check circuit in operating state, cpu in operating state (700khz rc oscillation stop) - 55 150 a 1 *: at non-regulated lcd driver. in case of select a voltage regulated lcd driver, see p.37/51.
fedl64p168-01 semiconductor ML64P168 29/51 dc characteristics (3.0 v spec. ) ( continued ) ( v ss =0v, v dd1 =1.5v, v dd2 =v ddi =v dd =3.0v, v dd3 =4.5v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit i oh1 v oh1 = v ddi - 0.5v -6.0 -1.7 -0.7 i ol1 v ol1 = 0.5v 2 5 20 i oh1s v ddi = 5.0v, v oh1s = v ddi - 0.5v -9 -3 -1 output current 1 ( p1.0 ) i ol1s v ddi = 5.0v, v ol1s = 0.5v 4 8 25 i oh2 v oh2 = v ddi - 0.5v -6.0 -2.0 -0.7 i ol2 v ol2 = 0.5v 0.7 2.0 6.0 i oh2s v ddi = 5.0v, v oh2s = v ddi - 0.5v -9 -3 -1 output current 2 ( p1.1 to p1.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) i ol2s v ddi = 5.0v, v ol2s = 0.5v 1 3 9 i oh3 v oh3 = v dd - 0.7v -6.0 -2.0 -0.7 output current 3 ( bd ) i ol3 v ol3 = 0.7v 0.7 6.0 10.0 i oh4 v oh4 = v dd - 0.1v -2.5 -0.8 -0.3 output current 4 ( rt0, rt1, rs0, rs1, crt0, cs0, cs1 ) i ol4 v ol4 = 0.1v 0.7 1.3 2.5 i oh5 v oh5 = v ddi - 0.5v -1.5 -0.8 -0.15 i ol5 v ol5 = 0.5v 0.15 2.0 4.0 i oh5s v ddi = 5v, v oh5s = v ddi - 0.5v -2.0 -1.5 -0.2 output current 5 ( when the pins l26 to l33 are configured as output ports ) i ol5s v ddi = 5v, v ol5s = 0.5v 0.2 3.0 5.0 i oh6 v oh6 = v dd - 0.5v -4.0 -0.8 -0.3 output current 6 ( osc2 ) i ol6 v ol6 = 0.5v 0.7 3.0 6.0 ma 2 i oh7 v oh7 = v dd3 - 0.2v (v dd3 level) - - -4 i omh7 v omh7 = v dd2 + 0.2v (v dd2 level) 4 - - i omh7s v omh7s = v dd2 - 0.2v (v dd2 level) - - -4 i oml7 v oml7 = v dd1 + 0.2v (v dd1 level) 4 - - i oml7s v oml7s = v dd1 - 0.2v (v dd1 level) - - -4 output current 7 ( l0 to l33 ) i ol7 v ol7 = v ss + 0.2v (v ss level) 4 - - i ooh v oh = v dd --0.3 output leakage current ( p1.0 to p1.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) (rt0, rt1, rs0, rs1, crt0, cs0, cs1 ) i ool v ol = v ss -0.3 - - a -
fedl64p168-01 semiconductor ML64P168 30/51 dc characteristics (3.0 v spec. ) ( continued ) (v ss =0v, v dd1 =1.5v, v dd2 =v ddi =v dd =3.0v, v dd3 =4.5v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit i ih1 v ih1 = v ddi ( when pulled down ) 30 90 300 i il1 v il1 = v ss ( when pulled up ) -300 -90 -30 i ih1s v ih1 = v ddi = 5v ( when pulled down ) 80 250 800 i il1s v il1 = v ss , v dd = 5v ( when pulled up ) -800 -250 -80 i ih1z v ih1 = v ddi ( in a high impedance ) 0 - 1 input current 1 ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) i il1z v il1 = v ss (in a high impedance ) -1 - 0 i ih2 v ih2 = v dd ( when pulled down ) 30 90 300 i ih2z v ih2 = v dd ( in a high impedance ) 0 - 1 input current 2 ( in0, in1 ) i il2z v il2 = v ss ( in a high impedance ) -1 - 0 i il3 v il3 = v ss ( when pulled up ) -300 -110 -10 i ih3z v ih3 = v dd ( in a high impedance ) 0 - 1 input current 3 ( osc1 ) i il3z v il3 = v ss ( in a high impedance ) -1 - 0 i ih4 v ih4 = v dd 0-1 a input current 4 ( reset, tst1, tst2 ) i il4 v il4 = v ss -3.00 -1.50 -0.75 ma 3 v ih1 - 2.4 - 3.0 v il1 -0-0.6 v ih1s v ddi = 5.0v 4 - 5 input voltage 1 ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) v il1s v ddi = 5.0v 0 - 1 v ih2 - 2.4 - 3.0 input voltage 2 ( in0, in1, osc1 ) v il2 -0-0.6 v ih3 - 2.4 - 3.0 input voltage 3 ( reset, tst1, tst2 ) v il3 -0-0.6 v4
fedl64p168-01 semiconductor ML64P168 31/51 dc characteristics (3.0 v spec. ) ( continued ) (v ss =0v, v dd1 =1.5v, v dd2 =v ddi =v dd =3.0v, v dd3 =4.5v, ta=0 to +65 c unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit ? v t1 - 0.2 0.5 1.0 hysteresis width ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) ? v t1s v ddi =5.0v 0.25 1.00 1.50 hysteresis width ( reset, tst1, tst2 ) ? v t2 - 0.2 0.5 1.0 v4 input pin capacitance ( p0.0 to p0.3 ) ( p2.0 to p2.3 ) ( p3.0 to p3.3 ) ( p4.0 to p4.3 ) c in ---5pf1
fedl64p168-01 semiconductor ML64P168 32/51 measuring circuit 1 v ss osc1 r os xt xt 32.768khz crystal c 12 c1 c2 c a ,c b ,c c ,c 12 r os r t0 c s0 r i0 : : : : : 0.1 f 60k ? 10k ? /2k ? 820pf 10k ? osc2 r t0 c s0 r i0 in0 cs0 rt0 a v ddi v dd v dd2 v v dd3 v c a c b v dd1 v c c measuring circuit 2 v dd v dd3 v dd2 v dd1 v ss v ih input *1 v il a *2 output v ddi
fedl64p168-01 semiconductor ML64P168 33/51 measuring circuit 3 v dd v dd3 v dd2 v ss a *3 input output v dd1 v ddi measuring circuit 4 v dd v dd3 v dd2 v dd1 v ss v ih *3 v il *1 input logic circuit to determine the specified measuring conditions. *2 measured at the specified output pins. *3 measured at the specified input pins. input output waveform monitoring v ddi
fedl64p168-01 semiconductor ML64P168 34/51 a/d converter characteristics (3.0 v spec. ) ( v ss =0v, v ddi =v dd =3.0v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measur- ing circuit resistor for oscillation r s0 , r s1 , r t0 , r t0-1 , r t1 c s0 , c t0 , c s1 740pf 1-- k ? input current limiting resistor r i0 , r i1 -110- k ? f osc1 resistor for oscillation =2 k ? 200 239 277 khz f osc2 resistor for oscillation =10 k ? 46.5 55.4 64.3 khz oscillation frequency f osc3 resistor for oscillation =200 k ? 2.79 3.32 3.85 khz kf1 r t0 , r t0-1 , r t1 = 2 k ? 4.272 4.380 4.490 - kf2 r t0 , r t0-1 , r t1 = 10 k ? 0.990 1.000 1.010 - rs ? rt oscillation frequency ratio(*) kf3 r t0 , r t0-1 , r t1 = 200 k ? 0.0573 0.0616 0.0659 - 5 * kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor in the same condition. f oscx (rt0 - cs0 oscillation) f oscx (rt0-1 - cs0 oscillation) f oscx (rt1 - cs1 oscillation) kfx= f oscx (rs0 - cs0 oscillation) , f oscx (rs0 - cs0 oscillation) , f oscx (rs1 - cs1 oscillation) (x=1, 2, 3)
fedl64p168-01 semiconductor ML64P168 35/51 measuring circuit 5 r t1 (crosc1) r s1 c s1 r i1 rt1 rs1 cs1 in1 r i0 c s0 r s0 in0 cs0 rs0 c t0 r t0 rt0 crt0 r t0-1 (crosc0) p0.0 p0.1 p0.2 p0.3 oscillation mode designation reset tst1 tst2 v ss d.u.t p4.3 frequency measurement (f oscx ) r t0 ,r t0-1 ,r t1 =2k ? /10k ? /200k ? r s0 ,r s1 =10k ? r i0 ,r i1 =10k ? c s0 ,c t0 ,c s1 =820pf v dd v ddi
fedl64p168-01 semiconductor ML64P168 36/51 ac characteristics ( 3.0v spec. ) ( serial interface ) ( v ss =0v, v dd2 =v dd =3.0v, v ddi =5.0v , ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit sclk input fall time t f - - 15 50 ns sclk input rise time t r - - 15 50 ns sclk input ?l? level pulse width t cwl -0.8-- s sclk input ?h? level pulse width t cwh -0.8-- s sclk input cycle time t cyc -2.0-- s sclk output cycle time t cyc1(o) cpu is operating at 32.768khz - 30.5 - s sclk output cycle time t cyc2(o) cpu is operating at 700khz - 1.43 - s sout output delay time t ddr ---0.4 s sin input setup time t ds -0.5-- s sin input hold time t dh -0.8-- s synchronous communication timing ( ?h? level = 4.0v, ?l? level = 1.0v ) t r t f t cwh t cwl t ddr t ddr t cyc t ds t ds t dh 5v 5v 5v sclk (p4.2) sout (p4.0) sin (p3.3)
fedl64p168-01 semiconductor ML64P168 37/51 recommended operating conditions ( when voltage regulator for lcd driver used ) (v ss = 0v) parameter symbol condition rating unit operating temperature t op -0 to + 65 c operating voltage v dd - 2.7 to 3.5 v crystal oscillation frequency f xt - 30 to 66 khz electrical characteristics ( when voltage regulator for lcd driver used ) dc characteristics (v ss =0v, v dd =3.0v, ta=0 to +65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit measur- ing circuit v dd1 v dd =2.7 to 3.5, ta=25 c 1.00 1.2 1.4 v v dd1 vo l t a g e ? v dd1 ---4- mv/ c v dd2 vo l t a g e v dd2 v dd =2.7 to 3.5 typ. - 0.1 2 v dd1 typ. + 0.1 v dd3 vo l t a g e v dd3 v dd =2.7 to 3.5 typ. - 0.2 3 v dd1 typ. + 0.2 v v dd =1.5v , cpu in halt state - 2 5 supply current 1 i dd1 v dd =3.0v, cpu in halt state - 7 12 v dd =1.5v, cpu in operating state - 15 30 supply current 2 i dd2 v dd =3.0v, cpu in operating state - 35 50 a 1 notes: the other electrical characteristics are the same as those for the 1.5v and 3.0v specifications.
fedl64p168-01 semiconductor ML64P168 38/51 power supply circuit v dd c1 c2 v dd3 v dd2 v dd1 v ss ML64P168 1.5v c s c 12 c c c b ML64P168 1.5v version v ddi c i 2.7 to 5v v dd c1 c2 v dd3 v dd2 v dd1 v ss ML64P168 3.0v c s c 12 c c ML64P168 3.0v version c a v ddi c i v dd c1 c2 v dd3 v dd2 v dd1 v ss ML64P168 1.5v c s c 12 c c ML64P168 1.5v version (the lcd bias is regulated.) c b v ddi c i 2.7 to 5v c a v dd c1 c2 v dd3 v dd2 v dd1 v ss ML64P168 3.0v c s c 12 c c ML64P168 3.0v version (the lcd bias is regulated.) c b note:c a ,c b ,c c ,c s ,c i ,c 12 :0.1 f +100% -50% v ddi c i c a
fedl64p168-01 semiconductor ML64P168 39/51 prom mode absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit prom power supply voltage v cc v cc =v dd , ta=25 c -0.3 to + 6.7 v program voltage v pp ta = 25c -0.3 to + 14.0 v prom input voltage v i v cc system input, ta=25 c -0.3 to v cc + 0.3 v prom output voltage v o v cc system output, ta=25 c -0.3 to v cc + 0.3 v storage temperature t stg - -55 to + 150 c recommended operating conditions (v ss = 0v) parameter symbol condition rating unit operating temperature t op -0 to + 65 c v cc power supply voltage v cc v cc =v dd =v ddi 4.75 to 5.25 v in read 4.75 to 5.25 v v pp power supply voltage v pp in write 12.0 to 13.0 v v ih v cc =v dd =v ddi 4 to v cc v input voltage v il -0 to 1v
fedl64p168-01 semiconductor ML64P168 40/51 read operation ( prom mode ) dc characteristics (v dd =v pp =5.0v 5%, ta=25 5 c unless otherwise specified ) parameter symbol condition min. typ. max. unit v cc power supply current (standby) i cc1 v cc = v dd ce =v ih --35ma v cc power supply current (operation) i cc2 v cc = v dd ce =v il - - 100 ma v ih v cc = v dd 4-v cc v input voltage v il -0-1 v i oh v cc = v dd v oh = v cc - 0.5v -2.0 -0.7 -0.2 ma output voltage i ol v ol = 0.5v 0.2 0.7 2.0 ma ac characteristics (v cc =5.0v 5%, v pp =v cc , ta=0 to 65 c unless otherwise specified ) parameter symbol condition min. typ. max. unit address access time t acc oe = ce =v il - - 120 ns ce access time t ce oe =v il - - 120 ns oe access time t oe ce =v il - - 50 ns output disable time t df ce =v il 0 - 40 ns measurement conditions: input pulse level 0.45 to 4.55v input rise / fall time 5ns timing judgement level input 0.8v, 2v / output 0.8v , 2v timing chart tce address input ce oe toe tdf tacc data output
fedl64p168-01 semiconductor ML64P168 41/51 write operation ( prom mode ) dc characteristics ( v ss =0v, v dd =5.0v 5%, v pp =12.5v 5v, ta=25 5 c unless otherwise specified ) parameter symbol condition min. typ. max. unit v pp power supply current i pp ce =v il --50ma v cc power supply current i cc v cc = v dd - - 100 ma v ih v cc = v dd 4-v cc v input voltage v il -0-1 v i oh v cc = v dd v oh = v cc - 0.5v -2.0 -0.7 -0.2 ma output voltage i ol v ol = 0.5v 0.2 0.7 2.0 ma ac characteristics ( v ss =0v, v dd =5.0v 5%, v pp =12.5 5v, ta=25 5 c unless otherwise specified ) parameter symbol condition min. typ. max. unit address set-up time t as -2-- s oe set-up time t oes -2-- s data set-up time t ds -2-- s address hold time t ah -0-- s data hold time t dh -2-- s oe output floating delay time t dep - 0 - 130 ns vpp power supply set-up time t vs -2-- s initial program pulse width t pw v dd =v ddi 6v 0.25v 0.95 1.0 1.05 ms additional program pulse width t opw v dd1 =v dd2 6v 0.25v 2.85 - 78.75 ms oe output effective delay time t oe - - - 150 ns measurement conditions: input pulse level 0.45 to 4.55v input rise / fall time less than 20ns timing judgement level input 0.8v, 2v / output 0.8v , 2v
fedl64p168-01 semiconductor ML64P168 42/51 program timing chart data output t as address input ce data input/output data input t ds t dh t vs t pw t opw t ah t dep t oe t oes oe v pp address n
fedl64p168-01 semiconductor ML64P168 43/51 functional description cpu peripheral function ? a/d converter ( adc ) the ML64P168 has a built-in two-channel rc oscillation a/d converter. the a/d converter is composed of a two-cannel oscillation circuit, counter a ( cnta0-4, a 4.8-digit decade counter ), counter b ( cntb0-3, a 14-bit binary counter ), and a/d converter control registers 0 and 1 ( adcon0, adcon1 ). by counting oscillation frequencies that vary depending on a resistor or capacitor connected to the rc oscillation circuit, the a/d converter converts resistance values or capacitance values to corresponding digital values. by using a thermistor or humidity sensor as a resistance, a thermometer or a hygrometer can be constructed. by applying a separate sensor to each cannel of the 2-channel rc oscillation circuit, it is also possible to extend measure ranges or measure at two places. ? serial port ( siop ) the ML64P168 has an 8-bit synchronous serial port. receive/transmit operation of the serial port is performed simultaneously and the serial transfer clock can select either internal or external mode. direction of transfer data can be big endian or little endian. each pin of the serial port is assigned as secondary functions of p3.3 and p4.0 to p4.2. setting each bit of sin,sout, spr and sclk of p33con and p40con to p42con to ?1? makes each pin valid. ? lcd driver ( lcd ) the ML64P168 has a built-in lcd driver for 34 outputs. the lcd driver consists of 31 4-bit display registers ( dspr0-30 ), the display control register ( dspcon ), a 34-output lcd driver circuit, and a bias generation circuit ( bias ). the bias generation circuit for lcd driver ( bias ) generates bias voltages for the lcd driver by rising or dropping the power supply voltage by externally installing capacitors. alternatively, it generates bias voltages by rising the constant voltage ( v dd1 = 1.2v ) generated by the voltage regulator for lcd driver. which way is to be used is specified by mask option. there are three types of driving methods: 1/4duty, 1/3duty and 1/2duty. software selects the duty mode. a mask option can select either a common driver or a segment driver for each lcd driver pin. a mask option can also specify assignment of each bit of the display register to each segment. all the display registers must be selected by a mask option. l26 to l33 of the lcd driver can be configured to be output ports by a mask option. the relationship between the duty, the bias method, and the maximum segment number follows: 1/4duty, 1/3 bias method ----------- 120 segments 1/3duty, 1/3 bias method ----------- 93 segments 1/2duty, 1/2 bias method ----------- 64 segments ? buzzer driver ( bd ) the ML64P168 has a built-in buzzer driver with 15 buzzer output frequencies and 4 buzzer output modes. each buzzer output is selected by the buzzer control register ( bdcon ) and the buzzer frequency control register ( bfcon ).
fedl64p168-01 semiconductor ML64P168 44/51 ? capture circuit ( capr ) the ML64P168 captures 32hz to 256hz output of the time base counter at the falling of port 0.0 or port 0.1 ( p0.0 or p0.1 ) to ?l? level when the pull-up resistor input is chosen, or at the rising to ?h? level when the pull-down resistor input is chosen. the capture circuit is composed of the capture control register ( capcon ) and the capture registers ( capr0, capr1 ) that fetch output from the time base counter. ? watchdog timer ( wdt ) the ML64P168 has a built-in watchdog timer to detect cpu malfunction. the watchdog timer is composed of a 6-bit watchdog timer counter ( wdtc ) to count a 16hz output and a watchdog timer control register ( wdtcon ) to reset wdtc. ? clock generation circuit ( 2clk ) the clock generation circuit ( 2clk ) in the ML64P168 contains a 32.768khz crystal oscillation circuit, a 700khz rc oscillation circuit, and a clock control port. this circuit generates the system clock ( clk ) and the time base clock ( 32.768khz ). the system clock drives the cpu while the time base clock drives the time base counter and the buzzer driver. via the contents of the frequency control register ( fcon ), the system clock can be switched between 32.768khz ( the output of the crystal oscillation circuit ) and 700khz ( the output of the rc oscillation circuit ). note: the oscillation frequency of the rc oscillation circuit varies depending on the value of an external resistor ( r os ), operating power supply voltage ( v dd ), and ambient temperatures (ta). ? time base counter ( tbc ) the ML64P168 has a built-in time base counter ( tbc ) that generates clocks to be supplied to internal peripheral circuit. the time base counter is composed of 15 binary counters, and a 1/10 frequency dividing circuit. the count clock of the time base is driven by the oscillation clock ( 32.768khz ) of the crystal oscillation circuit. the output of the time base counter is used for the buzzer driver, the system reset circuit, the watchdog timer, the time base interrupt, the sampling clocks of each port, and the capture circuit. ? i/o port input-output ports ( p2, p3, p4 ) : 3 ports 4bits pull-up ( pull-down ) resistor input or high-impedance input, cmos output or nmos open drain output: these can be specified for each bit; external 0 interrupt input port ( p0 ) : 1 port 4bits pull-up ( pull-down ) resistor input or high-impedance input; external 1 interrupt output port ( p1 ) : 1 port 4bits cmos output or nmos open drain output
fedl64p168-01 semiconductor ML64P168 45/51 ? interrupt ( intc ) the ML64P168 has 10 interrupt sources ( 10 vector address ), of which two are external interrupts from ports and eight are internal interrupts. of the ten interrupt sources, only the watchdog timer interrupt cannot be disabled ( non-maskable interrupt ). the other nine interrupts are controlled by the master interrupt enable flag ( mi ) and the interrupt enable registers ( ie0, ie1, and ie2 ). when an interrupt condition is met, the cpu branches to a vector address corresponding to the interrupt source. ? battery check circuit ( bc ) the battery check circuit ( bc ) detects the level of the supply voltage by comparing the voltage generated by an external supply-voltage dividing resistor ( r bld ) with the internal reference voltage ( v rb ).
fedl64p168-01 semiconductor ML64P168 46/51 application circuits (1.5 v spec. ) switch matrix ( 4 x 4 ) 32.768 khz r os c i 5v c s 1.5v c c c 12 c b ri0 cs0 rs0 rt0 ri1 cs1 rs1 rt1 buzzer c gex - 5v interface - temperature measurement by two thermistors - battery check circuit is used. - c gex of crystal oscillator : external v ddi v dd c2 c1 v dd3 v dd2 v ss v dd1 v pp tst2 tst1 lcd osc2 osc1 xt xt reset p1.0 p1.1 p1.2 p1.3 p0.0 p0.1 p0.2 p0.3 l33 l0 ml 64p168-xxxga/gp ml 64p168-xxx (1.5v spec.) p3.3 p4.0 p4.1 p4.2 p4.3 bd rt1 rs1 cs1 in1 rt0 crt0 rs0 cs0 in0 p3.1 r bld 1.5v spec. application circuit ( voltage regulator for lcd driver not used )
fedl64p168-01 semiconductor ML64P168 47/51 application circuits (1.5 v spec. ) ( continued ) switch matrix ( 4 x 4 ) 32.768 khz r os c i 5v c s 1.5v c c c 12 c b ri0 cs0 rs0 rt0 ri1 cs1 rs1 rt1 buzzer c gex - 5v interface - temperature measurement by two thermistors - battery check circuit is used. - c gex of crystal oscillator : external v ddi v dd c2 c1 v dd3 v dd2 v ss v dd1 v pp tst2 tst1 lcd osc2 osc1 xt xt reset p1.0 p1.1 p1.2 p1.3 p0.0 p0.1 p0.2 p0.3 l33 l0 ml 64p168-xxxga/gp (1.5v spec.) p3.3 p4.0 p4.1 p4.2 p4.3 bd rt1 rs1 cs1 in1 rt0 crt0 rs0 cs0 in0 p3.1 r bld c a 1.5v spec. application circuit ( voltage regulator for lcd driver used )
fedl64p168-01 semiconductor ML64P168 48/51 application circuits (3.0 v spec. ) switch matrix ( 4 x 4 ) 32.768 khz r os c i 5v c s 3v c c c 12 c a ri0 cs0 rs0 rt0 ri1 cs1 rs1 rt1 osc monitor sclk spr sout sin to the serial communication interface ( 5v ( v ddi ) system ) buzzer c gex - 5v interface - temperature measurement by two thermistors - battery check circuit is used. - c gex of crystal oscillator : external v ddi v dd c2 c1 v dd3 v dd2 v ss v dd1 v pp tst2 tst1 lcd osc2 osc1 xt xt reset p1.0 p1.1 p1.2 p1.3 p0.0 p0.1 p0.2 p0.3 l33 l0 ml 64p168-xxxga/gp (3.0v spec.) p3.3 p4.0 p4.1 p4.2 p4.3 bd rt1 rs1 cs1 in1 rt0 crt0 rs0 cs0 in0 p3.1 r bld 3.0v spec. application circuit ( voltage regulator for lcd driver not used )
fedl64p168-01 semiconductor ML64P168 49/51 application circuits (3.0 v spec. ) ( continued ) switch matrix ( 4 x 4 ) 32.768 khz r os c i 5v c s 3v c c c 12 c a ri0 cs0 rs0 rt0 ri1 cs1 rs1 rt1 osc monitor sclk spr sout sin to the serial communication interface ( 5v ( v ddi ) system ) buzzer c gex - 5v interface - temperature measurement by two thermistors - battery check circuit is used. - c gex of crystal oscillator : external v ddi v dd c2 c1 v dd3 v dd2 v ss v dd1 v pp tst2 tst1 lcd osc2 osc1 xt xt reset p1.0 p1.1 p1.2 p1.3 p0.0 p0.1 p0.2 p0.3 l33 l0 ml 64p168-xxxga/gp (3.0v spec.) p3.3 p4.0 p4.1 p4.2 p4.3 bd rt1 rs1 cs1 in1 rt0 crt0 rs0 cs0 in0 p3.1 r bld c b 3.0v spec. application circuit ( voltage regulator for lcd driver used )
fedl64p168-01 semiconductor ML64P168 50/51 package dimensions ML64P168- xxx gp figure c-1 80-pin qfp:gp package dimension diagram notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 0.05~0.35 2.5typ. 1.380.15 1.3typ. 2.10.2 2.5max. 0~10 0.25 24 1 25 80 20.00.2 25.00.2 0.8typ. 0.8 0.32 0.16 m index mark 64 65 40 41 14.00.2 19.00.2 1.0typ. -0.07 +0.08 0.170.05 0.12 seating plane
fedl64p168-01 semiconductor ML64P168 51/51 package dimensions ML64P168- xxx ga figure c-2 80-pin qfp:ga package dimension diagram notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 0.10 seating plane 0.170.05 2.10.2 2.4max. 0~0.25 0~10 0.25 0.670.15 0.6typ. 1.40.2 20 1 21 80 0.83typ. 0.65 index mark 60 61 40 41 14.00.1 16.80.2 0.83typ. 0.32 0.13 m -0.07 +0.08

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